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MX28F1000P
1M-BIT [128K x 8] CMOS FLASH MEMORY FEATURES
* 131,072 bytes by 8-bit organization * Fast access time: 70ns(Vcc:5V5%; CL:35pF) 90/120ns(Vcc:5V10%; CL:100pF) * Low power consumption - 50mA maximum active current - 100uA maximum standby current * Programming and erasing voltage 12V 5% * Command register architecture - Byte Programming (15us typical) - Auto chip erase 5 seconds typical (including preprogramming time) - Block Erase * Optimized high density blocked architecture - Four 4-KB blocks - Seven 16-KB blocks * Auto Erase (chip & block) and Auto Program - DATA polling - Toggle bit * 10,000 minimum erase/program cycles * Latch-up protected to 100mA from -1 to VCC+1V * Advanced CMOS Flash memory technology * Compatible with JEDEC-standard byte-wide 32-pin EPROM pinouts * Package type: - 32-pin plastic DIP - 32-pin PLCC - 32-pin TSOP (Type 1)
GENERAL DESCRIPTION
The MX28F1000P is a 1-mega bit Flash memory organized as 128K bytes of 8 bits each. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX28F1000P is packaged in 32-pin PDIP, PLCC and TSOP. It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers. The standard MX28F1000P offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX28F1000P has separate chip enable (CE) and output enable (OE ) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX28F1000P uses a command register to manage this functionality, while maintaining a standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX28F1000P uses a 12.0V 5% VPP supply to perform the Auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
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MX28F1000P Block Address and Block Structure
A16 A15 1 1 1 1 1 1 1 1 A14 A13 1 1 1 1 1 1 0 0 A12 1 0 1 0 A[16:0] 1FFFF 1F000 1EFFF 1E000 1DFFF 1D000 1CFFF 1C000 1BFFF
4k 4k 4k 4k 16k
1
1
0
X
X
18000 17FFF 1 0 1 X X
16k
14000 13FFF
1
0
0
X
X
16k
10000 0FFFF
0
1
1
X
X
16k
0C000 0BFFF
0
1
0
X
X
16k
08000 07FFF
0
0
1
X
X
16k
04000 03FFF
0
0
0
X
X
16k
00000
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PIN CONFIGURATIONS
32 PDIP
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3
TSOP (TYPE 1)
A11 A9 A8 A13 A14 NC WE VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3
MX28F1000P
MX28F1000P
(NORMAL TYPE)
32 PLCC
OE A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 A14 NC WE VCC VPP A16 A15 A12 A7 A6 A5 A4
VCC
VPP
A12
A15
A16
WE
A7 A6 A5 A4 A3 A2 A1 A0 Q0
5
4
1
32
30 29
NC
A14 A13 A8 A9
MX28F1000P
9
MX28F1000P
25
A11 OE A10 CE
13 14 Q1 Q2 VSS
17 Q3 Q4 Q5
21 20 Q6
Q7
(REVERSE TYPE)
PIN DESCRIPTION:
SYMBOL A0~A16 Q0~Q7 CE OE WE VPP VCC GND PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Write enable Pin Program Supply Voltage Power Supply Pin (+5V) Ground Pin
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BLOCK DIAGRAM
CE OE WE
CONTROL INPUT LOGIC
PROGRAM/ERASE HIGH VOLTAGE
MODE LOGIC
STATE
MX28F1000P FLASH ARRAY ARRAY SOURCE HV
X-DECODER
REGISTER
ADDRESS LATCH A0-A16 AND BUFFER
Y-PASS GATE
COMMAND DATA DECODER
Y-DECODER
SENSE AMPLIFIER
PGM DATA HV
COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q7
I/O BUFFER
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AUTOMATIC PROGRAMMING The MX28F1000P is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm does not require the system to time out or verify the data programmed. The typical room temperature chip programming time of the MX28F1000P is less than 5 seconds. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to only write an erase set-up command and erase command. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verify, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the erase operation.
AUTOMATIC CHIP ERASE
The device may be erased using the Automatic Erase algorithm. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internal to the device. Commands are written to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification, the MX28F1000P is designed to support either WE or CE controlled writes. During a system write cycle, addresses are latched on the falling edge of WE or CE whichever occurs last. Data is latched on the rising edge of WE or CE whichever occur first. To simplify the following discussion, the WE pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE signal. MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX28F1000P electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
AUTOMATIC BLOCK ERASE The MX28F1000P is block(s) erasable using MXIC's Auto Block Erase algorithm. Block erase modes allow blocks of the array to be erased in one erase cycle. The Automatic Block Erase algorithm automatically programs the specified block(s) prior to electrical erase. The timing and verification of electrical erase are controlled internal to the device.
AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the user to only write a program set-up command and a program command (program data and address). The device automatically times the programming pulse width, provides the program verify, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation.
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TABLE 1. COMMAND DEFINITIONS
COMMAND BUS CYCLES Read Memory Read Identified codes Setup auto erase/ auto erase (chip) Setup auto erase/ auto erase (block) 1 2 2 FIRST BUS CYCLE OPERATION Write Write Write ADDRESS X X X DATA 00H 90H 30H Read Write IA X ID 30H SECOND BUS CYCLE OPERATION ADDRESS DATA
2
Write
X
20H
Write
EA
D0H
Setup auto program/ program Setup Erase/ Erase (chip) Setup Erase/ Erase (block) Erase verify Reset
2
Write
X
40H
Write
PA
PD
2
Write
X
20H
Write
X
20H
2
Write
X
60H
Write
EA
60H
2 2
Write Write
EVA X
A0H FFH
Read Write
X X
EVD FFH
Note: IA = Identifier address EA = Block of memory location to be erased PA = Address of memory location to be programmed ID = Data read from location IA during device identification PD = Data to be programmed at location PA EVA = Address of memory location to be read during erase verify. EVD = Data read from location EVA during erase verify. Auto modes have the build-in enchanced features. Please use the auto erase mode whenever it is.
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COMMAND DEFINITIONS
When low voltage is applied to the VPP pin, the contents of the command register default to 00H, enabling read-only operation. Placing high voltage on the VPP pin enables read/write operations. Device operations are selected by writing specific data patterns into the command register. Table 1 defines these MX28F1000P register commands. Table 2 defines the bus operations of MX28F1000P. TABLE 2. MX28F1000P BUS OPERATIONS
OPERATION READ-ONLY Read Output Disable Standby Read Silicon ID (Mfr)(2) Read Silicon ID (Device)(2) READ/WRITE Read Standby(5) Write VPP(1) VPPL VPPL VPPL VPPL VPPL VPPH VPPH VPPH A0 A0 X X VIL VIH A0 X A0 A9 A9 X X VID(3) VID(3) A9 X A9 CE VIL VIL VIH VIL VIL VIL VIH VIL OE VIL VIH X VIL VIL VIL X VIH WE VIH VIH X VIH VIH VIH X VIL DQ0-DQ7 Data Out Tri-State Tri-State Data = C2H Data = 1AH Data Out(4) Tri-State Data In(6)
NOTES: 1. VPPL may be grounded, a no-connect with a resistor tied to ground, or < VCC + 2.0V. VPPH is the programming voltage specified for the device. When VPP = VPPL, memory contents can be read but not written or erased. 2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1. All other addresses are don't care.
3. VID is the Silicon-ID-Read high voltage.(11.5V to 13v) 4. Read operations with VPP = VPPH may access array data or Silicon ID codes. 5. With VPP at high voltage, the standby current equals ICC + IPP (standby). 6. Refer to Table 1 for valid Data-In during a write operation. 7. X can be VIL or VIH.
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READ COMMAND
While VPP is high, for erase and programming, memory contents can also be accessed via the read command. The read operation is initiated by writing 00H into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. The default contents of the register upon VPP powerup is 00H. This default value ensures that no spurious alteration of memory contents occurs during the VPP power transition. Where the VPP supply is hard-wired to the MX28F1000P, the device powers up and remains enabled for reads until the command register contents are changed. device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verify command is required). The margin voltages are internally generated in the same manner as when the standard erase verify command is used. The Automatic set-up erase command is a commandonly operation that stages the device for automatic electrical erasure of all bytes in the array. Automatic set-up erase is performed by writing 30H to the command register. To command automatic chip erase, the command 30H must be written again to the command register. The automatic chip erase begins on the rising edge of the WE and terminates when the data on DQ7 is "1" and the data on DQ6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode.
SILICON-ID-READ COMMAND
Flash-memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer- and device-codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a desired systemdesign practice. The MX28F1000P contains a Silicon-ID-Read operation to supplement traditional PROMprogramming methodology. The operation is initiated by writing 90H into the command register. Following the command write, a read cycle from address 0000H retrieves the manufacturer code of C2H. A read cycle from address 0001H returns the device code of 1AH.
SET-UP AUTOMATIC BLOCK ERASE/ERASE COMMANDS
The automatic block erase does not require the device to be entirely pre-programmed prior to executing the Automatic set-up block erase command and Automatic block erase command. Upon executing the Automatic block erase command, the device automatically will program and verify the block(s) memory for an all-zero data pattern. The system is not required to provide any controls or timing during these operations. When the block(s) is automatically verified to contain an all-zero pattern, a self-timed block erase and verify begin. The erase and verify operations are complete when the data on DQ7 is "1" and the data on DQ6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Block Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). The margin
SET-UP AUTOMATIC CHIP ERASE/ERASE COMMANDS
The automatic chip erase does not require the device to be entirely pre-programmed prior to excuting the Automatic set-up erase command and Automatic chip erase command. Upon executing the Automatic chip erase command, the device automatically will program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are complete when the data on DQ7 is "1" at which time the
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voltages are internally generated in the same manner as when the standard erase verify command is used. The Automatic set-up block erase command is a command only operation that stages the device for automatic electrical erasure of selected blocks in the array. Automatic set-up block erase is performed by writing 20H to the command register. To enter automatic block erase, the user must write the command D0H to the command register. Block addresses are loaded into internal register on the 2nd falling edge of WE. Each successive block load cycles, started by the falling edge of WE, must begin within 30ms from the rising edge of the preceding WE. Otherwise, the loading period ends and internal auto block erase cycle starts. When the data on DQ7 is "1" and the data on DQ6 stops toggling for two consecutive read cycles, at which time auto erase ends and the device returns to the Read mode. Refer to page 2 for detailed block address.
SET-UP CHIP ERASE/ERASE COMMANDS
Set-up Chip Erase is a command-only operation that stages the device for electrical erasure of all bytes in the array. The set-up erase operation is performed by writing 20H to the command register. To commence chip erasure, the erase command (20H) must again be written to the register. The erase operation begins with the rising edge of the WE pulse. This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when high voltage is applied to the VPP pin. In the absence of this high voltage, memory contents are protected against erasure.
SET-UP BLOCK ERASE/ERASE COMMANDS
Set-up Block Erase is a command-only operation that stages the device for electrical erasure of all selected block(s) in the array. The set-up erase operation is performed by writing 60H to the command register. To enter block-erasure, the block erase command 60H must be written again to the command register. The block erase mode allows 1 to 8 blocks of the array to be erased in one internal erase cycle. Internally, there are 8 registers (flags) addressed by A14 to A16. First block address is loaded into internal registers on the 2-nd falling of WE. Each successive block load cycles, started by the falling edge of WE, must begin within 30ms from the rising edge of the preceding WE. Otherwise, the loading period ends and internal block erase cycle starts. When the data on DQ7 is "1" at which time auto erase ends and the device returns to the Read mode.
SET-UP AUTOMATIC PROGRAM/PROGRAM COMMANDS
The Automatic Set-up Program is a command-only operation that stages the device for automatic programming. Automatic Set-up Program is performed by writing 40H to the command register. Once the Automatic Set-up Program operation is performed, the next WE pulse causes a transition to an active programming operation. Addresses are internally latched on the falling edge of the WE pulse. Data is internally latched on the rising edge of the WE pulse. The rising edge of WE also begins the programming operation. The system is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin. The automatic programming operation is completed when the data read on DQ6 stops toggling for two consecutive read cycles and the data on DQ7 and DQ6 are equivalent to data written to these two bits, at which time the device returns to the Read mode (no program verify command is required).
ERASE-VERIFY COMMAND
After each erase operation, all bytes must be verified. The erase verify operation is initiated by writing A0H into the command register. The address for the byte to be verified must be supplied as it is latched on the falling edge of the WE pulse.
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The MX28F1000P applies an internally generated margin voltage to the addressed byte. Reading FFH from the addressed byte indicates that all bits in the byte are erased. The erase-verify command must be written to the command register prior to each byte verification to latch its address. The process continues for each byte in the array until a byte does not return FFH data, or the last address is accessed. In the case where the data read is not FFH, another erase operation is performed. (Refer to Set-up Erase/ Erase). Verification then resumes from the address of the last-verified byte. Once all bytes in the array have been verified, the erase step is complete. The device can be programmed. At this point, the verify operation is terminated by writing a valid command (e.g. Program Set-up) to the command register. The High Reliability Erase algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the MX28F1000P.
DATA POLLING-DQ7
The MX28F1000P also features Data Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed. While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to DQ7. Upon completion of the Automatic Program algorithm an attempt to read the device will produce the true data last written to DQ7. The Data Polling feature is valid after the rising edge of the second WE pulse of the two write pulse sequences. While the Automatic Erase algorithm is in operation, DQ7 will read "0" until the erase operation is completed. Upon completion of the erase operation, the data on DQ7 will read "1". The Data Polling feature is valid after the rising edge of the second WE pulse of two write pulse sequences. The Data Polling feature is active during Automatic Program/Erase algorithms.
RESET COMMAND
A reset command is provided as a means to safely abort the erase- or program-command sequences. Following either set-up command (erase or program) with two consecutive writes of FFH will safely abort the operation. Memory contents will not be altered. Should program-fail or erase-fail happen, two consecutive writes of FFH will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.
POWER-UP SEQUENCE
The MX28F1000P powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of a two-step command sequence. Power up sequence is not required.
SYSTEM CONSIDERATIONS WRITE OPERATON STATUS
TOGGLE BIT-DQ6
The MX28F1000P features a "Toggle Bit" as a method to indicate to the host sytem that the Auto Program/ Erase algorithms are either in progress or completed. While the Automatic Program or Erase algorithm is in progress, successive attempts to read data from the device will result in DQ6 toggling between one and zero. Once the Automatic Program or Erase algorithm is completed, DQ6 will stop toggling and valid data will be read. The toggle bit is valid after the rising edge of the second WE pulse of the two write pulse sequences. During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND, and between VPP and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on FLASH memory arrays, a 4.7uF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
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MX28F1000P
ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 & VPP VALUE -40oC to 85oC -65oC to 125oC -0.5V to 7.0V -0.5V to 7.0V -0.5V to 7.0V -0.5V to 13.5V NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change.
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance MIN. TYP MAX. 14 16 UNIT pF pF CONDITIONS VIN = 0V VOUT = 0V
READ OPERATION DC CHARACTERISTICS
SYMBOL ILI ILO IPP1 ISB1 ISB2 ICC1 ICC2 VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 -0.3(NOTE 1) 2.4 Operating VCC current PARAMETER Input Leakage Current Output Leakage Current VPP Current Standby VCC current 1 1 MIN. TYP MAX. 10 10 100 1 100 UNIT uA uA uA mA uA CONDITIONS VIN = GND to VCC VOUT = GND to VCC VPP = 5.5V CE = VIH CE = VCC + 0.3V IOUT = 0mA, f=1MHz IOUT = 0mA, f=11MHz
30(NOTE4) mA 50 0.8 VCC + 0.3 0.45 mA V V V V
IOL = 2.1mA IOH = -400uA
NOTES: 1. VIL min. = -1.0V for pulse width < 50 ns. VIL min. = -2.0V for pulse width < 20 ns. 2. VIH max. = VCC + 1.5V for pulse width < 20 ns If VIH is over the specified maximum value, read operation cannot be guaranteed.
3. Test condition: TA =-40C to 85 Vcc = 5V10%, Vpp = GND to Vcc, CL C, = 100pF(for MX28F1000P-90/12) TA = -40C to 85 Vcc = 5V10%, Vpp = GND to Vcc, CL C, = 35pF(for MX28F1000P-70) 4.ICC1=35mA for TA=-40C to 85C
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AC CHARACTERISTICS
28F1000P-70 SYMBOL tACC tCE tOE tDF tOH PARAMETER Address to Output Delay CE to Output Delay OE to Output Delay OE High to Output Float (Note1) Address to Output hold 0 0 MIN. MAX. 70 70 30 15 0 0 0 NOTE: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 28F1000P-90 MIN. MAX. 90 90 35 20 0 0 28F1000P-12 MIN. MAX. 120 120 50 30 UNIT ns ns ns ns ns CONDITIONS CE=OE=VIL OE=VIL CE=VIL CE=VIL CE=OE=VIL
TEST CONDITIONS: * Input pulse levels: 0.45V/2.4V * Input rise and fall times: < 10ns * Reference levels for measuring timing: 0.8V, 2.0V * 28F1000P-70:Vcc = 5V 5%, CL: 1TTL gate + 35pF(including scope and jig) * 28F1000P-70:Vcc = 5V 5%, CL: 1TTL gate + 35pF(including scope and jig) * Vpp = GND to Vcc
READ TIMING WAVEFORMS
ADDRESS
WE
CE
STANDBY MODE
ACTIVE MODE
tCE
STANDBY MODE
OE
tOE tACC tOH tDF
DATA OUT
DATA OUT VALID
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COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION DC CHARACTERISTICS
SYMBOL ILI ILO ISB1 ISB2 ICC1 (Read) ICC2 ICC3 (Program) ICC4 (Erase) ICC5 (Program Verify) ICC6 (Erase Verify) IPP1 (Read) IPP2 (Program) IPP3 (Erase) IPP4 (Program Verify) IPP5 (Erase Verify) VIL VIH Input Voltage -0.3 (Note 5) 2.4 VPP Current Operating VCC Current PARAMETER Input Leakage Current Output Leakage Current Standby VCC current 1 MIN. TYP MAX. 10 10 1 100 30 50 50 50 50 50 100 50 50 50 50 0.8 UNIT uA uA mA uA mA mA mA mA mA mA uA mA mA mA mA V CONDITIONS VIN=GND to VCC VOUT=GND to VCC CE=VIH CE=VCC 0.3V IOUT=0mA, f=1MHz IOUT=0mA, F=11MHz In Programming In Erase In Program Verify In Erase Verify VPP=12.6V In Programming In Erase In Program Verify In Erase Verify
VCC+0.3V V (Note 6)
VOL VOH
Output Voltage 2.4
0.45
V V
IOL=2.1mA IOH=-400uA
NOTES: 1. VCC must be applied before VPP and removed after VPP. 2. VPP must not exceed 14V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP=12V. 4. Do not alter VPP either VIL to 12V or 12V to VIL when CE=VIL. 5. VIL min. = -0.6V for pulse width < 20ns. 6. If VIH is over the specified maximum value, programming operation cannot be guranteed. 7. All currents are in RMS unless otherwise noted.(Sampled, not 100% tested.) 8. For 28F1000P-70, Vcc = 5V 5%, CL = 35pF; for 28F1000P90/12, Vcc = 5V 10%, CL = 100pF.
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AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 5V 10%, VPP =12V 5%
28F1000-70 SYMBOL PARAMETER
tVPS tOES tCWC tCEP tCEPH1 tCEPH2 tAS tAH tAH1 tDS tDH tCESP tCES tCESC tCESV tVPH tDF tDPA tAETC tAETB tAVT tBALC tBAL tCH tCS VPP setup time OE setup time Command programming cycle WE programming pulse width WE programming pluse width High WE programming pluse width High Address setup time Address hold time Address hold time for DATA POLLING Data setup time Data hold time
28F1000P-90 MIN.
100 100 90 45 20 100 0 45 0 45 10 100 0 100 6 100
28F1000P-12 MIN.
100 100 120 50 20 100 0 50 0 50 10 100 0 100 6 100
MIN.
100 100 70 40 20 100 0 40 0 40 10
MAX.
MAX.
MAX.
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns ns ns us ns
CONTIONS
CE setup time before DATA polling/toggle bit 100 CE setup time CE setup time before command write CE setup time before verify VPP hold time Output disable time (Note 3) DATA polling/toggle bit access time Total erase time in auto chip erase Total erase time in auto block erase Total programming time in auto verify Block address load cycle Block address load time CE Hold Time CE setup to WE going low 0 100 6 100 15 70 5(TYP.) 5TYP.) 15 0.3 200 0 0 300 30
20 90 5(TYP.) 5(TYP.) 15 0.3 200 0 0 300 30 5(TYP.) 5(TYP.) 15 0.3 200 0 0
30 120
ns ns s s
300 30
us us us ns ns
NOTES: 1. CE and OE must be fixed high during VPP transition from 5V to 12V or from 12V to 5V. 2. Refer to read operation when VPP=VCC about read operation while VPP 12V. 3. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
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SWITCHING TEST CIRCUITS
DEVICE UNDER TEST
1.8K ohm +5V
CL 6.2K ohm
DIODES = IN3064 OR EQUIVALENT
CL = 100 pF including jig capacitance(35pF for 70 ns parts)
SWITCHING TEST WAVEFORMS
2.4 V 2.0V TEST POINTS 0.8V 0.45 V INPUT 0.8V OUTPUT 2.0V
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are <20ns.
P/N: PM0340
REV. 1.6, JAN. 19, 1999
15
MX28F1000P
AUTOMATIC PROGRAMMING TIMING WAVEFORM
One byte data is programmed. Verify in fast algorithm and additional programming by external control are not required because these operations are excuted automatically by internal control circuit. Programming completion can be verified by DATA polling and toggle bit checking after automatic verify starts. Device outputs DATA during programming and DATA after programming on Q7. Q0 to Q5 (Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) are in high impedance.
Setup auto program/ program command Vcc 5V 12V Vpp 0V A0 ~ A16 WE tCWC CE tOES OE tDS Q7 tDH tDS tDH tDPA DATA DATA polling tDF DATA tCEP tCEPH1 tCEP tCESP tCES tCESC tAS tAH1 tAVT Auto program & DATA polling
tVPH tVPS Address valid
Command in
Data in
Q0~Q5
Command in Command #40H
Data in
DATA
P/N: PM0340
REV. 1.6, JAN. 19, 1999
16
MX28F1000P
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Apply VppH
Write Set up auto program Command (40H)
Write Auto program Command(A/D)
Toggle Bit Checking DQ6 not Toggled YES
NO
Verify Byte Ok YES
NO
NO
Reset Last Byte YES
Auto Program Completed
Auto Program Failed
P/N: PM0340
REV. 1.6, JAN. 19, 1999
17
MX28F1000P
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verify is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7. Q0 to Q5 (Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) are in high impedance.
Setup auto chip erase/ erase command Vcc 5V 12V Vpp 0V A0 ~ A16 WE tCWC CE tOES OE tDS Q7 tDH tDS tCEP tCEPH1 tCEP tVPS
Auto chip erase & DATA polling
tVPH
tAETC
tCESP tCES
tCESC
tDH
tDPA
tDF
Command in
Command in DATA polling
Q0~Q5
Command in Command #30H
Command in Command #30H
P/N: PM0340
REV. 1.6, JAN. 19, 1999
18
MX28F1000P
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Apply VppH
Write Set up auto chip Erase Command (30H)
Write Auto chip Erase Command(30H)
Toggle Bit Checking DQ6 not Toggled YES
No
DATA Polling DQ7 = 1 YES
No
Reset
Auto Chip Erase Completed
Auto Chip Erase Failed
P/N: PM0340
REV. 1.6, JAN. 19, 1999
19
MX28F1000P
AUTOMATIC BLOCK ERASE TIMING WAVEFORM
Block data indicated by A12 to A16 are erased. External erase verify is not required because data are erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7. Q0 to Q5 (Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) are in high impedance.
Setup auto block erase/erase command
Auto block erase & DATA polling
Vcc 5V 12V Vpp 0V A0 ~ A11
tVPS tVPH
A12 ~ A16
tCH
Block address 0
Block address 1
Block address # tAH1
CE
tCS tAS tCWC tAH tBALC tBAL tAETB tCESC
WE
tOES
tCEPH1 tCEP tCEP tCEPH2
OE
tDS tDH tDS tDH tDPA tDF
Q7
Command in
Command in
DATA polling
Q0~Q5
Command in
Command in
Command #20H Command #D0H
*Refer to page 2 for detailed block address.
P/N: PM0340
REV. 1.6, JAN. 19, 1999
20
MX28F1000P
AUTOMATIC BLOCK ERASE ALGORITHM FLOWCHART
START
Apply VppH
Write Set up auto block Erase Command (20H)
Write Auto block Erase Command(D0H) to Load Block Address
Load Block Address
Last Block to Erase YES
NO
Wait 200us
Toggle Bit Checking DQ6 not Toggled YES
NO
DATA Polling DQ7 = 1 YES
NO
Reset
Auto Block Erase Completed Auto Block Erase Failed
P/N: PM0340
REV. 1.6, JAN. 19, 1999
21
MX28F1000P
COMPATIBLE CHIP ERASE TIMING WAVEFORM
All data in chip are erased. Control verification and additional erasure externally according tocompatible chip erase flowchart.
Setup chip erase/ erase command Chip erase Erase Verify
Vcc 5V 12V Vpp 0V
tVPS
Verify Address
tVPH
A0 ~ A16 WE
tCWC tET
tAS tAH
tCESV
CE
tOES tCEP tCEPH1 tCEP tCEP tCES tCESC
OE
tDS tDH tDS tDH tDS tDH tVA tDF
Data valid
Q7
Command in
Command in
Command in
Q0~Q6
Command in
Command in
Command in
Data valid
Command #20H Command #20H
Command #A0H
P/N: PM0340
REV. 1.6, JAN. 19, 1999
22
MX28F1000P
COMPATIBLE BLOCK ERASE
This device can be applied to the compatible block erase algorithm shown in the following flowchart. This algorithm allows to obtain faster erase time by the block (16K byte
COMPATIBLE BLOCK ERASE FLOWCHART
x 8 block) without any voltage stress to the device nor deterioration in reliability of data.
START
For selected block(s), All bits PGM"0"
N=0
BLOCK ERASE FLOW N = N+1
FAIL ERSVFY FLOW N = 1024? YES BLOCK ERASE FAIL APPLY VPP = VCC END
NO
ALL BITS VERIFIED
BLOCK ERASE COMPLETE
BLOCK ERASE FLOW
START
Apply VPP = VPPH
WRITE SETUP BLOCK ERASE COMMAND ( 60H )
WRITE BLOCK ERASE COMMAND ( LOAD FIRST SECTOR ADDRESS , 60H )
LOAD OTHER SECTORS' ADDRESS IF NECESSARY ( LOAD OTHER SECTOR ADDRESS )
WAIT 10 ms
END
P/N: PM0340
REV. 1.6, JAN. 19, 1999
23
MX28F1000P
ERASE VERIFY FLOW
START
APPLY VPP = VPPH
ADDRESS = FIRST ADDRESS OF ERASED BLOCKS OR LAST VERIFY FAILED ADDRESS
WRITE ERASE VERIFY COMMAND ( A0H )
WAIT 6 us
INCREMENT ADDRESS
ERSVFY FFH ?
NO
YES NO LAST ADDRESS ?
YES ERASE VERIFY COMPLETE GO TO ERASE FLOW AGAIN OR ABORT
P/N: PM0340
REV. 1.6, JAN. 19, 1999
24
MX28F1000P
COMPATIBLE BLOCK ERASE TIMING WAVEFORM
Indicated block data (16 Kbyte) are erased. Control verification and additional erasure externally according to compatible block erase flowchart.
Setup block erase/erase command
Block erase
Erase Verify
Vcc 5V 12V Vpp 0V A0 ~ A13
tVPS
Verify address
tVPH
A14 ~ A16
Block address 0
Block address 1
Block address #
Verify address
tAS tAH
tAS tAH
WE
tCWC tBALC tBAL tET tCESV
CE
tOES tCEP tCEPH1 tCEP tCEPH2 tCEP tCESC tCES
OE
tDS tDH tDS tDH tDS tDH tVA
Data valid
tDF
Q7
Command in
Command in
Command in
Q0~Q6
Command in
Command in
Command in
Data valid
Command #60H Command #60H
Command #A0H
P/N: PM0340
REV. 1.6, JAN. 19, 1999
25
MX28F1000P
VPP HIGH READ TIMING WAVEFORM
Vcc 5V 12V Vpp 0V A0 - A16
tVPS
tVPH
Address valid
tCWC
WE
tACC tCESC
CE
tOES tOES tCEP tCEPH1 tCE tDF tDS tDH
OE
tOE
tOH
Q0-Q7
Command in
00H
Data out valid
VPP LOW ID CODE READ TIMING WAVEFORM
VID VIH A9 VIL A0
A1 - A8 A10-A16
tACC
WE CE
VIH
tACC
tCE
OE
tDF tOE tOH tOH
Q0 - Q7
Manufacturer code C2H
Device code 1AH
P/N: PM0340
REV. 1.6, JAN. 19, 1999
26
MX28F1000P
VPP HIGH ID CODE READ TIMING WAVEFORM
Vcc 5V 12V Vpp 0V A0
tVPS
tVPH
Address Valid 0 or 1
A1 - A16
tCWC
WE
tACC tCESC
CE
tOES tOES tCEP tCEPH2 tCE
OE
tDF tDS tDH tOE tOH
Q0-Q7
Command in
90H
Data out valid
C2H or 1AH
RESET TIMING WAVEFORM
Vcc 5V 12V Vpp 0V A0 - A16 WE
tCWC
tVPS
CE
tOES tCEP tCEPH1 tCEP
OE
tDS tDH
tDS
tDH
Q0-Q7
Command in
FFH
Command in
FFH
P/N: PM0340
REV. 1.6, JAN. 19, 1999
27
MX28F1000P
TOGGLE BIT, DATA POLLING TIMING WAVEFORM Toggle bit appears in Q6, when program/erase is opperating. DATA polling appears in Q7 during programming or erase.
HIGH
WE Vpp 12V CE
OE
Q6 DURING P/E Q7 DURING P Q7 DURING E Q0~Q5
HIGH-Z
TOGGLE BIT DATA DATA POLLING
HIGH-Z DATA HIGH-Z DATA DATA PROGRAM/ERASE COMPLETE DATA
HIGH-Z
DATA POLLING DATA
ERASE AND PROGRAMMING PERFORMANCE LIMITS PARAMETER Chip/Sector Erase Time Chip Programming Time Erase/Program Cycles Byte Program Time 10,000 15 642 MIN. TYP. 1.5 2 MAX. 20 13.8 UNITS sec sec cycles us
P/N: PM0340
REV. 1.6, JAN. 19, 1999
28
MX28F1000P
ORDERING INFORMATION PLASTIC PACKAGE
PART NO. ACCESS TIME OPERATING CURRENT (ns) MX28F1000PPC-70C4 MX28F1000PPC-90C4 MX28F1000PPC-12C4 MX28F1000PQC-70C4 MX28F1000PQC-90C4 MX28F1000PQC-12C4 MX28F1000PTC-70C4 70 90 120 70 90 120 70 MAX.(mA) 50 50 50 50 50 50 50 STANDBY CURRENT MAX.(uA) 100 100 100 100 100 100 100 32 Pin DIP 32 Pin DIP 32 Pin DIP 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC 32 Pin TSOP (Normal Type) MX28F1000PTC-90C4 90 50 100 32 Pin TSOP (Normal Type) MX28F1000PTC-12C4 120 50 100 32 Pin TSOP (Normal Type) MX28F1000PRC-70C4 70 50 100 32 Pin TSOP (Reverse Type) MX28F1000PRC-90C4 90 50 100 32 Pin TSOP (Reverse Type) MX28F1000PRC-12C4 120 50 100 32 Pin TSOP (Reverse Type) MX28F1000PPI-70 MX28F1000PPI-90 MX28F1000PPI-12 MX28F1000PQI-70 MX28F1000PQI-90 MX28F1000PQI-12 MX28F1000PTI-70 70 90 120 70 90 120 70 50 50 50 50 50 50 50 100 100 100 100 100 100 100 32 Pin DIP 32 Pin DIP 32 Pin DIP 32 Pin PLCC 32 Pin PLCC 32 Pin PLCC 32 Pin TSOP (Normal Type) MX28F1000PTI-90 90 50 100 32 Pin TSOP (Normal Type) MX28F1000PTI-12 120 50 100 32 Pin TSOP (Normal Type) MX28F1000PRI-70 70 50 100 32 Pin TSOP (Reverse Type) MX28F1000PRI-90 90 50 100 32 Pin TSOP (Reverse Type) MX28F1000PRI-12 120 50 100 32 Pin TSOP (Reverse Type) 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 PACKAGE ERASE/PROGRAM CYCLE MIN.(time) 10,000 10,000 10,000 10,000 10,000 10,000 10,000
P/N: PM0340
REV. 1.6, JAN. 19, 1999
29
MX28F1000P
PACKAGE INFORMATION
32-PIN PLASTIC DIP
ITEM A B C D E F G H I J K L M
MILLIMETERS 42.13 max. 1.90 [REF] 2.54 [TP] .46 [Typ.] 38.07 1.27 [Typ.] 3.30 .25 .51 [REF] 3.94 .25 5.33 max. 15.22 .25 13.97 .25 .25 [Typ.]
INCHES 1.660 max. .075 [REF] .100 [TP] .050 [Typ.] 1.500 .050 [Typ.] .130 .010 .020 [REF] 1.55 .010 .210 max. .600 .101 .550 .010 .010 [Typ.]
F D E C B M 0~15 H G I J 1 A 16 K L 32 17
NOTE: Each lead certerline is located within .25mm[.01 inch] of its true position [TP] at a maximum at maximum material condition.
32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
A
ITEM A B C D E F G H I J K L
MILLIMETERS 12.44 .13 11.50 .13 14.04 .13 14.98 .13 1.93 3.30 .25 2.03 .13 .51 .13 1.27 [Typ.] .71 [REF] .46 [REF] 10.40/12.94 (W) (L)
INCHES .490 .005 .453 .005 .553 .005 .590 .005 .076 .130 .010 .080 .005 .020 .005 .050 [Typ.] .028 [REF] .018 [REF] .410/.510 (W) (L) .035R .010[Typ.]
F G 13 14 9 5 4
B 1
32
30 29
25
C
D
21 20 E N
17
M N
.89R .25[Typ.]
NOTE: Each lead certerline is located within .25mm[.01 inch] of its true position [TP] at a maximum at maximum material condition.
H I K L M J
P/N: PM0340
REV. 1.6, JAN. 19, 1999
30
MX28F1000P
32-PIN PLASTIC TSOP
ITEM A B C D E F G H I J K L M N MILLIMETERS 20.0 .20 18.40 .10 8.20 max. 0.15 [Typ.] .80 [Typ.] .20 .10 .30 .10 .50 [Typ.] .45 max. 0 ~ .20 1.00 .10 1.27 max. .50 0 ~5 INCHES .078 .006 .724 .004 .323 max. .006 [Typ.] .031 [Typ.] .008 .004 .012 .004 .020 [Typ.] .018 max. 0 ~ .008 .039 .004 .050 max. .020 .500
D E
NOTE: Each lead certerline is located within .25mm[.01 inch] of its true position [TP] at a maximum at maximum material condition.
A B
C
O M N
K J
L
F
G
H
I
P/N: PM0340
REV. 1.6, JAN. 19, 1999
31
MX28F1000P
Note. Revision History Revision # Description 1.4 Fast access time 150ns and 1,000 times erase cycles removed. Tsop pin configuration diagram rotated 180. The flow chart of block erase corrected. 1.5 Fast access time 70ns added. 1.6 1)Absolute max. ratings:TA=-40C to 85C 2)DC Characteristics:ICC1=35mA for TA=-40C to 85C 3)AC Characteristics:TA=-40C to 85C 4)Order Informance:Add Industrial Grade 5)Erase & Programming Performance:New in Creased table Page Date
P11 P14 P29
Dec/26/1996 JAN/19/1999
P/N: PM0340
REV. 1.6, JAN. 19, 1999
32
MX28F1000P
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888 FAX:+886-3-578-8887
EUROPE OFFICE:
TEL:+32-2-456-8020 FAX:+32-2-456-8021
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TEL:+81-44-246-9100 FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-747-2309 FAX:+65-748-4090
TAIPEI OFFICE:
TEL:+886-3-509-3300 FAX:+886-3-509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
33

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